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RM0008
Flexible static memory controller (FSMC)
Bits 7:4 ADDHLD: Address-hold phase duration.
These bits are written by software to define the duration of the address hold phase (refer to
Figure 170 to Figure 172 ), used in SRAMs, ROMs and asynchronous multiplexed NOR Flash
accesses:
0000: Reserved
0001: ADDHLD phase duration = 2 × HCLK clock cycle
0010: ADDHLD phase duration = 3 × HCLK clock cycle
...
1111: ADDHLD phase duration = 16 × HCLK clock cycles (default value after reset)
Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always
1 Flash clock period duration.
Bits 3:0 ADDSET: Address setup phase duration.
These bits are written by software to define the duration of the address setup phase in HCLK
cycles (refer to Figure 170 to Figure 172 ), used in SRAMs, ROMs and asynchronous multiplexed
NOR Flash:
0000: ADDSET phase duration = 1 × HCLK clock cycle
...
1111: ADDSET phase duration = 16 × HCLK clock cycles (default value after reset)
Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always
1 Flash clock period duration.
19.6
NAND Flash/PC Card controller
The FSMC generates the appropriate signal timings to drive the following types of device:
●
NAND Flash
–
–
8-bit
16-bit
●
16-bit PC Card compatible devices
The NAND/PC Card controller can control three external banks. Bank 2 and bank 3 support
NAND Flash devices. Bank 4 supports PC Card devices.
Each bank is configured by means of dedicated registers ( Section 19.6.7 ). The
programmable memory parameters include access timings (shown in Table 113 ) and ECC
configuration.
Doc ID 13902 Rev 9
441/995
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